The photomask holding back big AI dies gets bigger in 2031
Key takeaways
- ASML, TSMC, Samsung and Intel have aligned behind a move from 6x6 inch to 6x12 inch photomasks
- High-NA EUV's anamorphic optics halve the printable field to 26x16.5 mm, forcing stitching or chiplets
- A pilot line is targeted for 2031 with production nodes around 2033
- Nobody has settled who funds the R&D
Chips have been printed through a 6x6 inch stencil for roughly four decades. ASML, TSMC, Samsung and Intel have now lined up behind moving to 6x12.
That reads like a procurement footnote. It is actually the thing standing between High-NA EUV and the very large AI dies everyone wants to print, and the fix does not arrive until the early 2030s.
Why a bigger stencil prints smaller chips
High-NA EUV gets its resolution from a wider numerical aperture, and the optics that deliver it are anamorphic. The lens demagnifies by 4X in one axis and 8X in the other, which is what buys the sharper print. The cost is field size.
Conventional EUV exposes a 26x33 mm field in one pass. High-NA halves that to 26x16.5 mm. A design that used to fit comfortably inside a single exposure now has to be printed as two stitched halves, or broken up into chiplets and reassembled in packaging.
Neither option is free. Stitching two exposures means aligning them to nanometre tolerances, and every misalignment is a dead die. That costs yield and throughput, and it costs money twice, once in wafer time and once in scrap. A 6x12 inch mask restores the full field and prints the die in a single pass, which is why four companies that agree on very little have agreed on this.
The timeline is the sobering part
A pilot line is targeted for 2031. Production nodes follow around 2033. Nobody has settled who funds the R&D, which is the detail that usually decides whether an industry roadmap holds or slips.
Between now and then, every giant accelerator is either stitched or chiplet-based. That is not a design preference, it is a ceiling. If you have wondered why recent flagship parts keep arriving as multi-die packages rather than one enormous monolith, this is a large part of the answer, alongside the yield economics covered in what a 2nm chip actually means.
What it means for the rest of the stack
Chiplet design is now a permanent competency rather than a transitional trick. That favours companies with strong packaging, which is one reason TSMC's advanced packaging capacity has become as contested as its leading-edge wafers. It also lowers the barrier for challengers, because a competitive chiplet is a smaller engineering bet than a competitive monolithic die, which is part of the context behind efforts like Alibaba's Zhenwu V900.
On the consumer side the effect is indirect but real. Mobile silicon has been chiplet-shy for power and area reasons, so parts like the Snapdragon 8 Elite Extreme Gen 6 stay well inside the High-NA field and are largely unaffected. The squeeze lands on the largest dies, which means data centre accelerators.
What to watch
Watch for a funding announcement, not a technical one. The physics here is settled and the engineering is understood. The open question is who pays for a mask infrastructure transition that benefits four competitors equally and no single one of them first.
If that answer has not arrived by 2028, the 2031 pilot date is optimistic, and the supply-side ceiling on single-pass AI silicon moves out with it.
