IBM crams 100 billion transistors onto one chip
Not by shrinking transistors further. By stacking them in layers and rethinking how they talk to each other.
IBM says its NanoStack architecture has hit a mark the industry has chased for years: 100 billion transistors on a single chip. The design delivers 50% better performance than the current generation while using 70% less energy. That second number is the one that matters most.
The trick is not making transistors smaller. Shrinking them further is getting physically brutal. NanoStack instead stacks them vertically in layers and redesigns how those layers communicate, moving past the limits of traditional flat 2D chip layouts. Early results suggest the approach has room to scale further still.
For everyday devices, chips like this eventually filter down into phones, laptops and everything else. But the first and biggest impact will be in AI inference hardware, where electricity is the dominant operating expense. A 70% energy cut at higher performance rewrites the cost curve for running models at scale.
That is why hyperscalers will care immediately. When you operate data centres full of accelerators, your power bill is the business. A chip that does more work for a third of the energy is not a spec-sheet curiosity, it is a direct line to lower running costs and fatter margins on every model served.
It is worth keeping expectations grounded. Lab numbers and shipping silicon are different things, and the path from architecture announcement to a chip you can buy is measured in years, not weeks. IBM also has commercial reasons to put its best foot forward. But even discounted, the direction is striking.
For a decade the story has been that Moore's Law was running out of road. NanoStack is one of the clearest recent signs that the semiconductor industry still has moves left. The headline transistor count grabs attention, but the energy number is what will move budgets.