Stacked transistors could make SRAM 52.7% smaller, on paper
Key takeaways
- Lam Research models a self-aligned CFET design with a 0.0094 um2 6T SRAM bit cell, 52.7% smaller than N3
- The result comes from digital twin modelling with at least a 10 nm overlay window, so no chips have been built yet
- CFET stacks one type of transistor on top of the other, which saves area by building upward rather than sideways
A 6T SRAM bit cell measuring 0.0094 square micrometres. That is the modelled result from Lam Research for a stacked transistor design, and it is 52.7% smaller than the same cell on N3. It is also a simulation, so no chip has been made this way yet.
What a CFET transistor is
Every logic chip is built from two kinds of transistor, n-type and p-type, which work as a pair. For decades they have sat side by side on the silicon. A CFET, short for complementary field effect transistor, stacks one on top of the other. Same pair, same job, a much smaller footprint.
A useful comparison is a car park. Shrinking each space only gets you so far. Building a second level doubles the cars without needing more ground. Chip makers are running out of ways to shrink flat transistors, so going vertical is the logical next step.
What Lam actually showed
Lam Research describes a self-aligned CFET architecture that could extend CMOS scaling below 10 angstroms, which is 1 nanometre. The figures come from digital twin modelling, meaning a detailed computer model of the manufacturing process rather than a real wafer.
The model gave the 0.0094 um2 bit cell, and it assumed an overlay window of at least 10 nm. Overlay is how precisely one layer lines up with the next, and in a stacked design it is the hard part. A wider window is more forgiving, so a result with at least 10 nm to spare is encouraging.
Why to read it carefully
SRAM is the fast memory built into processors, and it is one of the places where shrinking has already become difficult. A saving of this size would matter for any chip with large caches. It would not automatically shrink the whole chip, since logic and wiring do not scale in lockstep.
Modelled results routinely look better than manufactured ones. Real factories deal with defects, heat and cost, and stacking two layers of transistors adds steps to an already long process. This is a promising direction rather than a product.
The part worth watching is whether Lam, or chip makers working with it, can show working test structures. A real wafer with these dimensions would turn this from a good simulation into a roadmap. For background on how architectures differ at the instruction level, see our guide to RISC-V vs Arm vs x86.
