Co-Packaged Optics Explained: The AI Chip Bottleneck Is the Wiring

More than 100 terabits per second, per node. That is what an AI cluster now has to move between its GPUs, switches and memory systems, and it is the number that explains why the frontier is no longer limited by transistors. Copper cannot carry that. It has reached its physical ceiling, and the industry has known it for a while.

Moving the data costs more than doing the sums

The uncomfortable detail in current systems is the energy split. Shifting data between components can burn more power than the computation those components are doing. A GPU that spends most of its budget waiting for and ferrying numbers is not a compute problem, it is a plumbing problem.

That reframes a lot of hardware news from the past year. It is why AMD's Helios pitch led with 31TB of memory rather than FLOPS, why HBM4 gets the attention it does, and why Intel's Crescent Island turned up with 480GB as its headline figure. Feeding the chip is the hard part.

What co-packaged optics actually does

The response is to stop using copper for the longest and busiest links. Co-packaged optics puts silicon photonics inside the same package as the processor, so data leaves as light rather than as electrical signal on a trace. Light carries far more data per watt over distance, and it does not degrade the way copper does as frequency climbs.

In plain terms: instead of running the fibre to a transceiver on the edge of the board, the conversion happens millimetres from the die. The copper run that was the bottleneck stops existing.

SEMICON Taiwan 2026 ran in Taipei this week with more than 100,000 attendees from 65 countries, and it gave photonics its own pavilion alongside a Memory Executive Summit for HBM. Trade shows allocate floor space to whatever the money is chasing, which tells you where the constraint has moved.

The list of things holding AI back keeps growing

For a couple of years the shorthand for the AI supply crunch was wafer capacity at TSMC. That list is now considerably longer: CoWoS packaging, HBM supply, substrates, OSAT capacity, power, cooling, networking and optics. Any one of them can cap a deployment regardless of how many wafers are available.

That breadth is the reason semiconductor revenue forecasts for 2026 keep getting revised around data centre demand rather than consumer demand. Roughly half of industry revenue this year is expected to come from AI data centre chips, and most of that spending lands on the parts nobody used to write about.

The part worth sitting with is that none of this shows up in a benchmark. A cluster limited by its interconnect posts the same specification sheet as one that is not.